1. Field of the Invention
This invention relates to computers and computer system complexes comprising a logically partitioned processor governed by a hypervisor. More particularly, this invention describes a mechanism for coordinating the synchronization between an external timer, connected to physical processors in the processor complex, and logical processors controlled by a hypervisor executing on the physical processors.
2. Background Art
CPU time-of-day (TOD) clocks are well known in the data processing field. A time-of-day clock provides a high-resolution measure of real time suitable for the indication of date and time of day. In an installation with more than one CPU, each CPU may have a separate TOD clock, or more than one CPU may share a clock, depending on the model. In all cases, each CPU has access to a single clock.
The TOD clock in an embodiment such as IBM's ESA/390 Systems is a binary counter. The bit positions of the clock are numbered 0 to 63, corresponding to the bit positions of a 64-bit unsigned binary integer.
In the basic form, the TOD clock is incremented by adding a one in bit position 51 every microsecond. In models having a higher or lower resolution, a different bit position is incremented at such a frequency that the rate of advancing the clock is the same as if a one were added in bit position 51 every microsecond. The resolution of the TOD clock is such that the incrementing rate is comparable to the instruction-execution rate of the model.
A TOD clock is said to be in a particular multiprocessing configuration (i.e., tightly coupled MP system) if at least one of the CPUs which shares that clock is in the configuration. Thus, it is possible for a single TOD clock to be in more than one configuration. Conversely, if all CPUs having access to a particular TOD clock have been removed from a particular configuration, then the TOD clock is no longer considered to be in that configuration.
When more than one TOD clock exists in the configuration, the stepping rates are synchronized such that all TOD clocks in the configuration are incremented at exactly the same rate.
When incrementing of the clock causes a carry to be propagated out of bit position 0, the carry is ignored, and counting continues from zero. The program is not alerted, and no interruption condition is generated as a result of the overflow.
The operation of the clock is not affected by any normal activity or event in the system. Incrementing of the clock does not depend on whether the wait-state bit of the PSW is one or whether the CPU is in the operating, load, stopped, or check-stop state. Its operation is not affected by CPU, initial-CPU, or clear resets or by initial program loading. Operation of the clock is also not affected by the setting of the rate control or by an initial-microprogram-loading operation. Depending on the model and the configuration, a TOD clock may or may not be powered independent of a CPU that accesses it.
In an installation with more than one CPU, each CPU may have a separate TOD clock, or more than one CPU may share a TOD clock, depending on the model. In all cases, each CPU has access to a single clock.
The TOD-clock-synchronization facility of IBM's ESA/370 systems, in conjunction with a clock-synchronization program, makes it possible to provide the effect of all CPUs in a tightly coupled multiprocessing configuration sharing a single TOD clock. The result is such that, to all programs storing the TOD-clock value, it appears that all CPUs in the configuration read the same TOD clock. The TOD-clock-synchronization facility provides these functions in such a way that even though the number of CPUs sharing a TOD clock is model-dependent, a single model-independent clock-synchronization routine can be written. The following functions are provided:
Synchronizing the stepping rates for all TOD clocks in the configuration. Thus, if all clocks are set to the same value, they stay in synchronism. PA1 Comparing the rightmost 32 bits of each clock in the configuration. An unequal condition is signaled by an external interruption with the interruption code 1003 hex, indicating the TOD-clock-sync-check condition. PA1 Setting a TOD clock to the stopped state. PA1 Causing a stopped clock, with the TOD-clock-sync-control bit set to one, to start incrementing when bits 32-63 of any running clock in the configuration are incremented to zero. This permits the program to synchronize all clocks to any particular clock without requiring special operator action to select a "master clock" as the source of the clock-synchronization pulses.
In a logically partitioned processor, such as IBM's PR/SM-LPAR, a plurality of operating systems operate in logical partitions, with the partitions controlled by a hypervisor. Such an approach is described in U.S. Pat. No. 4,843,541, "Logical Resource Partitioning of a Data Processing System", by Bean, et al., assigned to the assignee of the present invention and incorporated by reference herein. In such an environment, each logical processor is typically provided with a logical TOD clock which is used as the target and source of set and store clock instructions, and is managed by the hypervisor.
An additional complexity is introduced in a loosely-coupled system configuration, which is to be kept in sync by an external timer source (such as IBM's Sysplex Timer Facility). Such an external timer is described in the following patent applications, which are assigned to the present assignee, and incorporated herein by reference: "Fault Tolerant Clock for Multicomputer Complex", Ser. No. 07/392,812, filed Aug. 11, 1989, by Appelbaum, et al., now U.S. Pat. No. 5,249,206 "External Time Reference With Dynamic Steering", Ser. No. 07/537,389, filed Jun. 12, 1990, by Moorman, et al. now U.S. Pat. No. 5,041,798. In this case, a mechanism is provided for synchronizing a plurality of physical processors with an external time source. This presents the need for a way of providing timer support, including synchronization, to one or more logical partitions (each having operating systems running), controlled by a hypervisor, when the partitions are physically running on one or more physical processors which may be synchronized with an external timer source.
It is therefore an object of the present invention to provide timer support for a logically partitioned DP system with physical (host) processors which may be synchronized with an external timer.
It is a further object of this invention to provide hypervisor support for logical partitions which contain operating systems which interact with and are aware of the existence of an external timer, while at the same time supporting logical partitioning containing systems which do not interact with and are not aware of the existence of an external timer, where both sets of logical partitions execute on a common set of physical processors.